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This page will contain a brief summary of each lecture given in the 2015-16 session of the Inf3 Computer Architecture course.
All slides from Lecture 1 were covered. To reinforce this lecture, read textbook sections 1.1 to 1.6. Use the web to search for additional information about the latest microprocessor offerings from the major manufacturers and try to cultivate an understanding of the state-of-the-art. To prepare for the next lecture, read textbook sections 1.8, 1.9 and 1.11 and do some background research into Amdahl's Law and the CPU Time Equation.
Thursday 14th January
All slides from Lecture 2 were covered. We discussed: relevant metrics for computer architects, particularly focusing on performance; quantifying performance and performance improvement through Amdahl's Law and the CPU Performance Equation. We also discussed basic ways of affecting performance.
Today we discussed ISA design, covering the first 12 slides of Lecture 3. To reinforce this lecture, you could read the following papers:
Thursday 21st January
Today we wrapped up Lecture 3 by discussing instructions for altering control flow and fundamental trade-offs in ISA design.
We reviewed pipelining, touching on important issues of pipeline balance and propagation of control signals, instruction operands & results from stage to stage via the pipeline registers. We then began discussing the three types of pipeline hazard (structural, control, data). We discussed the causes of structural hazards and began looking at the causes of data hazards. We convered until slide 22 from Lecture 4.
Thursday 28th January
Today we completed the material from Lecture 4. Then, we discussed the issue of how performance varies as the depth of the pipeline is increased. We watched the Apple Presentation of the G4 processor and how it compares with Pentium 4 (circa 2001): dubbed by Apple as Megahertx Myth. We then discussed this quantitatively. For more infromation about this topic, have a look at 3 ISCA papers (ISCA is the flagship conference of computer architecture) papers that appeared in 2002, all of which were attempting to compute the optimal pipeline depth! Paper 1. Paper 2. Paper 3.
We then started discussing advance topics in handling hazards, in particular those arising from multicycle operations; we covered until slide 10 from Lecture 5.
Thursday 4th February
Today's lecture focused on static and dynamic branch prediction. For a more in-depth study, you should read the original 1991 paper by Yeh and Patt (1991) Two-Level Adaptive Training Branch Prediction, from the Proceedings of the 24th Annual International Symposium on Microarchitecture. We covered all slides from Lecture 5.
We started discussing dynamic scheduling policies as a way of improving microprocessor performance. The key idea is to execute instructions out-of-order, which requires discovering and tracking dependencies across instructions. We discussed the three types of dependencies that need to be honoured (RAW, WAR, and WAW). We specifically discussed scoreboarding, one of the earliest dynamic scheduling techniques introduced in the CDC 6600 mainframe computer. Scoreboarding uses a set of centralized structures to track instructions in flight, functional unit status, and register status. It conservatively enforces WAW and WAR dependences and does not support forwarding. We covered until slide 7 from Lecture 6.
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