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This page will contain a brief summary of each lecture given in the 2011-2012 session of the Inf3 Computer Architecture course.
All slides from Lecture 1 were covered. To reinforce this lecture, you are advised to read sections 1.3 to 1.6. Use the web to search for additional information about the latest microprocessor offerings from the major manufacturers and try to cultivate an understanding of the state-of-the-art. To prepare for the next lecture you should read HP sections 1.8, 1.9 and 1.11 and, if time permits, do some background research into Amdahl's Law and the CPU Time Equation.
Thursday 19th January
All slides from Lecture 2 were covered.
We revised the last 2 slides of the previous lecture; we discussed the quantitative example of applying CPU performance equation again. We then started discussing ISA design -- the first 6 slides from Lecture 3 were covered.
Thursday 26th JanuaryThe remaining slides from Lecture 3 were covered. To prepare for the next lecture, you should read HP 4th edition section A.1 (5th edition section C.1).
We covered the basics of pipelining and pipeline representation, until slide 18 of Lecture 4. To prepare for the next lecture, you should read HP 4th edition section A.2 (5th edition section C.2).
Thursday 2nd FebruaryWe discussed pipeline hazards and discussed the 3 types of hazards: structural, data and control. We covered all the remaining slides from Lecture 4. To prepare for the next lecture, you should read HP 4th edition section A.3, A.5 and 2.3 (5th edition section C.3, C.5 and 3.3).
We discussed in detail how structural, data and control hazards are handled. We then discussed static and dynamic branch prediction strategies. We covered until slide slide 10 of Lecture 5. To prepare for the next lecture, you should read HP 4th edition C.1 (5th edition B.1). The CAR assignment was handed out today.
Thursday 9th FebruaryWe covered all the remaining slides from Lecture 5. We now take a detour into memory system architecture for a few lectures. We shall return to look in more depth at dynamic scheduling and out-of-order execution. We began by introducing the notion of localilty, both from a temporal and a spatial perspective. We then saw how a memory hierarchy can exploit locality to achieve the illusion of a fast, large memory. We explored the concept of a cache and showed how caches are constructed for Direct-Mapped, Set-Associative and Fully-Associative organisations. We convered until slide 8 of Lecture 6. To prepare for the next lecture, you should read HP 4th edition C.1 and C.2 (5th edition B.1 and B.2).
In this lecture we continued to discuss cache performance and in particular how to compute the impact of cache misses on overall CPI. A useful concept is AMAT (average memory access time), which can be computed from the hit time, miss ratio and the miss penalty. The 'three Cs' were introduced as a way to remember the three main causes of cache misses. We discussed a couple of techniques to reduce miss ratio: optimization of block size, and the use of hardware and software prefetching. We covered until slide 9 of Lecture 7.
Thursday 16th FebruaryIn this lecture, we continued with various other techniques for reducing the miss rate and miss penalty. We covered until slide 24 of Lecture 7. To prepare for the next lecture, you should read HP 4th edition C.3 and C.4 (5th edition B.3 and B.4).
No classes, Innovative Learning week.
Thursday 23rd FebruaryNo classes, Innovative Learning week.
In this lecture, we looked at a couple of techniques for reducing hit time: (b) having small and simple caches and (b) virtually indexed caches. To understand the second optimization better, we looked at virtual memory and address translation in more detail. We covered until slide 40 of Lecture 7.
Thursday 1st MarchIn this lecture, we summarised the different techniques for optimizing cache performance and started the discussion on Dynamic Scheduling. We completed Lecture 7 and covered until slide 5 of Lecture 8. To prepare for the next lecture, which will be on Thursday 8th March, you should read HP 4th edition A.7, 2.4, 2.5 (5th edition C.7, 3.4, 3.5)
No class today.
Thursday 8th MarchIn this lecture, we disussed the Scoreboarding technique for performing Dynamic Scheduling. We covered all slides in Lecture 8. To prepare for the next lecture you should read HP 4th edition 2.4, 2.5 (5th edition 3.4, 3.5)
In this lecture, we first discussed the limitations of the Scoreboarding technique, and then discussed the Tomasulo's Algorithm for performing Dynamic Scheduling. We covered all slides in Lecture 9.
Thursday 15th MarchIn this lecture, we discussed about processors which issue multiple instructions every cycle; more specifically we discussed about superscalar processors and VLIW processors. We also discussed how speculation can help in executing instructions past a branch, and how receovery can be performed upon a misprediction. We covered all slides in Lecture 10. The next lecture, which will be on Thursday 22nd March, will introduce you to multiprocessors.
No class today.
Thursday 22nd MarchThis lecture (the final lecture of the CAR course) was essentially a brief introduction to multiprocessors. We first discussed why they are commonplace nowadays. We then very briefly discussed some of the important issues associated with multiprocessors including: shared memory, message passing, cache coherency, and memory consistency. These topics would be discussed in more detail in the parallel computer architecture course. We briefly discussed all the slides in Lecture 11.
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