CS4/MSc Parallel Architectures - 2017-2018

Assignment 1: Due 2-2-2018, 4 PM (soft-copy using submit command)

This assignment will consist of a literature review for both CS4 and MSc students. This will contribute 5% of the final mark for this course. Feedback for this assignment will be available on or before 23-2-2018.

Material

• Handout
• Papers
  • (Paper A) ``Guest Editors' Introduction: Billion-Transistor Architectures'', D. Burger and J. R. Goodman, IEEE Computer, vol. 30, no. 9, September 1997.
  • (Paper B) ``A Single-Chip Multiprocessor'', L. Hammond, B. A. Nayfeh, and K. Olukotun, IEEE Computer, vol. 30, no. 9, September 1997.
  • (Paper C) ``One Billion Transistors, One Uniprocessor, One Chip'', Y. N. Patt, S. J. Patel, M. Evers, D. H. Friendly, and J. Stark, IEEE Computer, vol. 30, no. 9, September 1997.
  • (Paper C) ``Superspeculative Microarchitecture for Beyond AD 2000'', M. H. Lipasti and J. P. Shen, IEEE Computer, vol. 30, no. 9, September 1997.
  • (Paper C) ``Trace Processors: Moving to Fourth-Generation Microarchitectures'', J. E. Smith and S. Vajapeyam, IEEE Computer, vol. 30, no. 9, September 1997.
  • (Paper C) ``Scalable Processors in the Billion-Transistor Era: IRAM'', C. E. Kozyrakis, S. Perissakis, D. Patterson, T. Anderson, K. Asanovic, N. Cardwell, R. Fromm, J. Golbus, B. Gribstad, K. Keeton, R. Thomas, N. Treuhaft, and K. Yelick, IEEE Computer, vol. 30, no. 9, September 1997.
  • (Paper C) ``Baring It All to Software: Raw Machines'', E. Waingold, M. Taylor, D. Srikrishna, V. Sarkar, W. Lee, V. Lee, J. Kim, M. Frank, P. Finch, R. Barua, J. Babb, S. Amarasinghe, A. Agarwal, IEEE Computer, vol. 30, no. 9, September 1997.