Informatics Report Series


Aristeidis Efthymiou

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Report Date Title
EDI-INF-RR-1071 May 2007 Synthetic Trace-Driven Simulation of Cache Memory
EDI-INF-RR-1070 Mar 2007 A Hybrid Markov Model for Accurate Memory Reference Generation
EDI-INF-RR-0513 Dec 2005 Test Pattern Generation and Partial-Scan Methodology for an Asynchronous SoC Interconnect
EDI-INF-RR-0456 Jun 2004 Remedy for an asynchronous weakness: a fully-testable interconnect fabric
EDI-INF-RR-0455 Dec 2002 Adaptive Pipeline Depth for Asynchronous Systems Using Collapsible Latch Controllers
EDI-INF-RR-0454 Feb 2004 Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits
EDI-INF-RR-0453 Apr 2004 An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm
EDI-INF-RR-0452 Nov 2004 Adding Testability to an Asynchronous Interconnect for GALS SoCs
EDI-INF-RR-0451 Mar 2004 A CAM with mixed serial-parallel comparison for use in low energy caches
EDI-INF-RR-0450 May 2003 Adaptive Pipeline Structures for Speculation Control
EDI-INF-RR-0449 Aug 2002 An Adaptive Serial-Parallel CAM Architecture for Low-Power Cache Blocks
EDI-INF-RR-0448 Sep 2002 Adaptive Pipeline Depth Control for Processor Power-Management
EDI-INF-RR-0447 Jun 2002 Pipeline Occupancy Control for Power Adaptive Processors
EDI-INF-RR-0437 2005 Asynchronous On-Chip Networks
EDI-INF-RR-0433 Jul 2005 Fast, Parallel Two-Rail Code Checker with Enhanced Testability
EDI-INF-RR-0431 Mar 2001 Power Management in the AMULET Microprocessors
EDI-INF-RR-0430 Sep 2001 A Comparative Power Analysis of an Asynchronous Processor

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