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Title:Remedy for an asynchronous weakness: a fully-testable interconnect fabric
Authors: Aristeidis Efthymiou ; J. Bainbridge ; D. Edwards
Date:Jun 2004
Publication Title:Procs of 4th AciD-WG Workshop
Publication Type:Conference Paper
One of the greater strengths of asynchronous circuits is their potential for solving the interconnect problems faced by system-on-chip designers. As the area of a chip reachable in a single clock cycle is becoming smaller for each technology generation, asynchronous global interconnects for systems on chip are becoming an increasingly more attractive solution. CHAIN [1] is an architecture for system-on-chip interconnect using delay insensitive signalling and a message passing protocol. Connections are built from gangs of narrow signalling channels, each with its own acknowledge. Since completion detection over these narrow channels only requires the use of simple circuits and avoids the large trees of C elements found in conventional, wide datapaths, the links can operate at much higher speeds than the equivalent wide-datapath would be capable of. Although asynchronous techniques can efficiently solve the system on chip interconnection problems, the adoption of asynchronous design has been held back by a lack of methodology and support for fabrication testing of such circuits. This is commonly regarded as the most severe weakness of this class of circuits. A methodology, based on full-scan LSSD, proposed by Philips [2] can produce fully testable circuits. Although this method is as efficient as the standard synchronous equivalent for bundled-data type datapaths, it causes a significant area and speed overhead to control circuits. Essentially each feedback loop must be scanned, so every C element must be modified to include a scan-latch. For the QDI design style that CHAIN uses, the area overhead of this approach is unacceptable. In this presentation a partial-scan methodology is discussed where the vast majority of feedback loops, those inside C elements and SR latches, are not scanned . Thus, the generation of appropriate values in internal nodes to test for faults requires sequential patterns. This approach requires a modified LSSD scan-latch with
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Bibtex format
author = { Aristeidis Efthymiou and J. Bainbridge and D. Edwards },
title = {Remedy for an asynchronous weakness: a fully-testable interconnect fabric},
book title = {Procs of 4th AciD-WG Workshop},
year = 2004,
month = {Jun},

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