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Title:An Adaptive Serial-Parallel CAM Architecture for Low-Power Cache Blocks
Authors: Aristeidis Efthymiou ; J. D. Garside
Date:Aug 2002
Publication Title:Procs of ISLPED'02
Publication Type:Conference Paper
Page Nos:136-141
There is an on-going debate about which consumes less energy: a RAM-tagged associative cache with an intelligent order of accessing its tags and ways (e.g. way prediction), or a CAM-tagged high associativity cache. If a CAM search can consume less than twice the energy of reading a tag RAM, it would probably be the preferred option for low-power applications. Based on memory traces - which usually cause tag mismatch within the lower four bits - a new serial CAM organisation is proposed which consumes just 45% more than a single tag RAM read and is only 25% slower than the conventional, parallel CAM. Furthermore, it can optionally be operated as a parallel CAM, at no speed penalty, and still reduce energy consumption.
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Bibtex format
author = { Aristeidis Efthymiou and J. D. Garside },
title = {An Adaptive Serial-Parallel CAM Architecture for Low-Power Cache Blocks},
book title = {Procs of ISLPED'02},
year = 2002,
month = {Aug},
pages = {136-141},
url = {},

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