CS4/MSc Parallel Architectures - 2017-2018

Assignment 2: Due 6-3-2018, 4 PM (submission instructions in the handout)

In this programming assignment, which is for both CS4 and MSc students, you will develop a cache coherence protocol simulator. This will contribute 20% of the overall mark for this course. Feedback for this assignment will be available on or before 26-3-2017.



If you have questions related to this assignment, send an email to the TA: Arpit Joshi (also cc the course instructor Vijay Nagarajan).

Vijay Nagarajan, IF 1.22, ext. 513440