- Abstract:
-
This paper describes the use of simulations to study the limits on Instruction Level Parallelism (ILP) in a micronetbased asynchronous processor. The impact of two features on the exploitable ILP were studied: the dependency lengths between instructions in the program, and the asynchronous synchronisation overhead in the architecture. The results demonstrate that the attenuation in the speedup due to ILP is moderate with increases in the synchronisation overheads (of upto 50% of ALU computation cost), thanks to the overlapping of communication and computation inherent in micronet architectures.
- Links To Paper
- 1st Link
- Bibtex format
- @InProceedings{EDI-INF-RR-0534,
- author = {
D.K. Arvind
and C. Keepax
},
- title = {Limits on ILP in Micronet-based Architectures},
- book title = {Procs of 14th UK Asynchronous Forum},
- year = 2003,
- month = {Jun},
- url = {http://www.staff.ncl.ac.uk/i.g.clark/async/ukasyncforum14/forum14-papers/forum14-arvind.pdf},
- }
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