- Abstract:
-
This paper explores the idea of the processor as an asynchronous network, called the micronet, of functional units which compute concurrently and communicate asynchronously. A micronet-based asynchronous processor exposes spatial as well as temporal concurrency. We analyse the performance of the processor-as-a-network by comparing three scheduling algorithms for exploiting Instruction Level Parallelism (ILP). Schedulers for synchronous architectures have relied on deterministic instruction execution times. In contrast, ILP scheduling in micronet-based architectures is a challenge as it is less certain in advance when instructions start execution and when results become available. Performance results comparing the three schedulers are presented for SPEC95 benchmarks executing on a cycle-accurate model of the micronet architecture.
- Links To Paper
- 1st Link
- Bibtex format
- @InProceedings{EDI-INF-RR-0516,
- author = {
D.K. Arvind
and Sotelo Salazar
},
- title = {Scheduling for ILP in the `Processor-as-a-Network'},
- book title = {Procs of Communication Process Architectures},
- publisher = {IOS Press},
- year = 2003,
- month = {Sep},
- pages = {289-304},
- url = {http://wotug.org/paperdb/send_file.php?num=103},
- }
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