- Abstract:
-
We have in the past investigated the design and implementation of micronet-based architectures of the scalar[AR94], superscalar[AM99], VLIW[AS97] and Multithreaded[AHKR01] kind, which were all based on a RISC-like instruction set. In this paper, we present a preliminary design, based around a micronet core, of an asynchronous Complex Instruction Set Computer (CISC) architecture. A TRANSLATOR module converts the CISC instructions into ones which are native to the micronet datapath, called the milliops instructions. This translation can be accomplished either in hardware, as in Intel s x86 architectures, or in software, in the style of Transmeta s Crusoe architecture. The design environment enables C programs targeted at the CISC architecture, to be executed on a RTL model of the micronet core, and its execution and power consumption can be visualised over space and time. This allows a systematic study of the effect of compiler and architectural optimisations of micronet-based CISC processors, on the performance of application benchmarks.
- Links To Paper
- .ps file
- .pdf file from citeseer
- Bibtex format
- @InProceedings{EDI-INF-RR-0514,
- author = {
D.K. Arvind
and C. Bainbridge
},
- title = {Micronet-based CISC Architectures},
- book title = {Procs of 11th UK Asynchronous Forum},
- year = 2001,
- month = {Dec},
- url = {http://www.dcs.ed.ac.uk/home/dka/forum11.ps},
- }
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