- Abstract:
-
Asynchronous design offers a solution to the interconnect problems faced by system-on-chip designers, but their adoption has been held back by a lack of methodology and support for post-fabrication testing. This paper first addresses the problem of testing C-elements, an important building block of asynchronous circuits. A simple method for generating test patterns is described which is shown to be applicable for a wide range of implementations. Based on the C-element testability, a partial scan technique was developed that achieves a test coverage of over 99.5% when applied to an asynchronous, networkon-chip, interconnect fabric. Test patterns are automatically generated by a custom program, given the interconnect topology. Area savings of at least 60% are noted, in comparison to standard, asynchronous, full-scan LSSD methods.
- Links To Paper
- 1st Link
- Bibtex format
- @Article{EDI-INF-RR-0513,
- author = {
Aristeidis Efthymiou
and John Bainbridge
and Douglas Edwards
},
- title = {Test Pattern Generation and Partial-Scan Methodology for an Asynchronous SoC Interconnect},
- journal = {IEEE Transactions on VLSI Systems},
- publisher = {IEEE Computer Society},
- year = 2005,
- month = {Dec},
- volume = {13(12)},
- pages = {1384-1393},
- doi = {10.1109/TVLSI.2005.862722},
- url = {http://ieeexplore.ieee.org/iel5/92/33422/01583664.pdf},
- }
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