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Title:IATAC: A Smart Predictor to Turn-Off L2 Cache Lines
Authors: Jaume Abella ; Antonio Gonzlez ; Xavier Vera ; Michael O'Boyle
Date:Mar 2005
Publication Title:ACM Transactions on Architecture and Code Optimization
Volume No:2(1) Page Nos:55-77
As technology evolves, power dissipation increases and cooling systems become more complex and expensive. There are two main sources of power dissipation in a processor: dynamic power and leakage. Dynamic power has been the most significant factor, but leakage will become increasingly significant in future. It is predicted that leakage will shortly be the most significant cost as it grows at about a 5 rate per generation. Thus, reducing leakage is essential for future processor design. Since large caches occupy most of the area, they are one of the leakiest structures in the chip and hence, a main source of energy consumption for future processors. This paper introduces IATAC (inter-access time per access count), a new hardware technique to reduce cache leakage for L2 caches. IATAC dynamically adapts the cache size to the program requirements turning off cache lines whose content is not likely to be reused. Our evaluation shows that this approach outperforms all previous state-of-the-art techniques. IATAC turns off 65% of the cache lines across different L2 cache configurations with a very small performance degradation of around 2%.
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Bibtex format
author = { Jaume Abella and Antonio Gonzlez and Xavier Vera and Michael O'Boyle },
title = {IATAC: A Smart Predictor to Turn-Off L2 Cache Lines},
year = 2005,
month = {Mar},
volume = {2(1)},
pages = {55-77},
url = {},

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