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Title:Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits
Authors: Aristeidis Efthymiou ; C. Sotiriou ; D. Edwards
Date:Feb 2004
Publication Title:Procs of DATE'04
Publication Type:Conference Paper
Volume No:I Page Nos:672-773
This paper presents 3/spl Phi/LSSD, a novel, easily-automatable approach for scan insertion and ATPG of asynchronous circuits. 3/spl Phi/LSSD inserts scan latches only into global circuit feedback paths, leaving the local feedback paths of asynchronous state-storing gates intact. By employing a three-phase LSSD clocking scheme and complemented by a novel ATPG method, our approach achieves industrial quality testability with significantly less area overhead testing the same number of faults compared to full-scan LSSD. The effectiveness of our approach is demonstrated on an asynchronous SOC interconnection fabric, where our 3/spl Phi/LSSD ATPG tool achieved over 99% test coverage.
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Bibtex format
author = { Aristeidis Efthymiou and C. Sotiriou and D. Edwards },
title = {Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits},
book title = {Procs of DATE'04},
year = 2004,
month = {Feb},
volume = {I},
pages = {672-773},
url = {},

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