- Abstract:
-
Asynchronous circuits offer great potential for solving the interconnect problems faced by system-on-chip designers, but their adoption has been held back by a lack of methodology and support for fabrication testing of such circuits. This paper addresses this problem using a partial scan approach which achieves a test coverage of 99.5% on the CHAIN network-on-chip interconnect fabric which is used as an example. Test patterns are generated by a custom program automatically, given the topology of the interconnect. In comparison to standard, asynchronous, full-scan LSSD methods, area savings in the order of 50% are noted.
- Links To Paper
- 1st Link
- 2nd Link
- Bibtex format
- @InProceedings{EDI-INF-RR-0452,
- author = {
Aristeidis Efthymiou
and J Bainbridge
and D. Edwards
},
- title = {Adding Testability to an Asynchronous Interconnect for GALS SoCs},
- book title = {Procs of 2004 IEEE Asian Test Symposium (ATS'04)},
- year = 2004,
- month = {Nov},
- pages = {20-23},
- url = {ftp://ftp.cs.man.ac.uk/pub/amulet/papers/aris_test04_ieee.pdf},
- }
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