INF3 Computer Design

2017/2018

 
 

There are no tutorials for the Computer Design course. Instead, the coursework consists of a weekly three-hour laboratory session. The practicals are carried out in the level-3 laboratory in Appleton Tower, under the supervision of the lecturer and/or a lab demonstrator/tutor. The first practical is a tutorial to introduce you to the Xilinx systems design software used to program the FPGAs. The lab sessions begin with a very simple design to take you through all the stages of implementing logic in FPGAs. Along the way you will be introduced to the hardware description language, Verilog, and to the process of simulating a logic design described in Verilog. The second practical will follow the same design and implementation procedure for a specified combinational design. The third practical is an arithmetic circuit design and implementation as part of a larger circuit (VGA pipeline). Changes in the pipeline may be required to meet timing.


When you have finished each practical you must ask your lab demonstrator to record that fact, then you may proceed to the next practical. That way you can control your own time organisation. Information about using the Xilinx FPGA board and Verilog is contained in manuals placed in the laboratory. Formative feedback is provided by laborary demonstrators during laboratory sessions. They are there to help you understand the task, and may give hints regarding the solution, but you are expected to define your own solutions and write your own Verilog descriptions. Each practical is also assessed summatively. This takes the form of a mark for each practical that together contribute 25% of the overall course mark.


  1. Practical #1 : Introduction to Xilinx FPGA Design Tools
    Available : 25th Sept 2017
    Deadline : 9th Oct 2017 16:00
    Assignment, Labsheet, Marking scheme

    ZYBO default .xdc file (take a copy)
  2. Practical #2 : Adders, Multipliers, and State machines.
    Available : 2nd Oct 2017
    Deadline : 23rd Oct 2017 16:00
    Assignment, Labsheet, Marking scheme, Zipped Project

  3. Practical #3 : Memory Interfacing and Pipelined Functions.
    Available : 16th Oct 2017
    Deadline : 20th Nov 2017 16:00
    Assignment, Labsheet, Marking scheme, Zipped Project

  4. Laboratory Advice: Fixes for known problems
    1. Use the MATE desktop environment
    2. Reboot your lab machine if you cannot get a license for Vivado


Laboratory Groups

The laboratory groups will be set up at times shown at the top of this page. You can work at times other than your scheduled lab slot but there must be at least one other person in the lab at the same time and no other class using the lab at that time. The Lab sessions are from 2 to 5pm in the level-3 lab of Appleton Tower. Once assigned, the lab groups can be found here. Login to school of Informatics web portal may be required.


Marking

Each practical is worth a number of marks, contributing to the overall course practical mark. Practical one is worth 10 marks, practical 2 is worth 20 marks, practical 3 is worth 40 marks. Overall practical mark is thus out of 70.
Marking is based on showing the completed designs to a lab demonstrator and, for practicals 2 and 3, discussing the implemented designs in a report. If there is a report, there are more marks for the report than for merely demonstrating the completed design. The practical handouts contain guidance as to contents of each individual report.


Late Submissions and Extensions

The Informatics late submission policy applies to all Computer Design coursework. The ISS will apply a penalty of 5% per day, up to 7 calendar days, for late submissions. If you have a good reason to request an extension (e.g. illness) please contact ISS before the deadline, via the contact form. They may be able to extend your deadline by up to 7 days.

Practicals

Lab info